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HN58V256A Series HN58V257A Series
256k EEPROM (32-kword x 8-bit) Ready/Busy and RES function (HN58V257A)
REJ03C0147-0500Z (Previous ADE-203-357D (Z) Rev.4.0) Rev. 5.00 Nov. 17. 2003
Description
Renesas Technology's HN58V256A and HN58V257A are electrically erasable and programmable ROMs organized as 32768-word x 8-bit. They have realized high speed, low power consumption and high reliability by employing advanced MNOS memory technology and CMOS process and circuitry technology. They also have a 64-byte page programming function to make their write operations faster.
Features
* Single 3 V supply: 2.7 to 5.5 V * Access time: 120 ns max * Power dissipation: Active: 20 mW/MHz, (typ) Standby: 110 W (max) * On-chip latches: address, data, CE, OE, WE * Automatic byte write: 10 ms max * Automatic page write (64 bytes): 10 ms max * Ready/Busy (only the HN58V257A series) * Data polling and Toggle bit * Data protection circuit on power on/off * Conforms to JEDEC byte-wide standard * Reliable CMOS with MNOS cell technology * 10 erase/write cycles (in page mode)
5
* 10 years data retention * Software data protection * Write protection by RES pin (only the HN58V257A series) * Industrial versions (Temperature range: -20 to 85C and -40 to 85C) are also available. * There are free also lead free products.
Rev.5.00, Nov. 17.2003, page 1 of 22
HN58V256A Series, HN58V257A Series
Ordering Information
Type No. HN58V256AFP-12 HN58V256AT-12 HN58V257AT-12 HN58V256AFP-12E HN58V256AT-12E HN58V257AT-12E Access time 120 ns 120 ns 120 ns 120 ns 120 ns 120 ns Package 400 mil 28-pin plastic SOP (FP-28D) 28-pin plastic TSOP (TFP-28DB) 32-pin plastic TSOP (TFP-32DA) 400 mil 28-pin plastic SOP (FP-28DV) Lead Free 28-pin plastic TSOP (TFP-28DBV) Lead Free 32-pin plastic TSOP (TFP-32DAV) Lead Free
Pin Arrangement
HN58V256AFP Series A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (Top view) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 A10 15 16 17 18 19 20 21 22 23 24 25 26 27 28 (Top view) HN58V257AT Series A2 A1 A0 NC I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 NC A10 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (Top view) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A3 A4 A5 A6 A7 A12 A14 RDY/Busy VCC HN58V256AT Series 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A3 A4 A5 A6 A7 A12 A14 VCC
WE
A13 A8 A9 A11
OE
A10
WE OE
CE
I/O7 I/O6 I/O5 I/O4 I/O3
CE
A13 A8 A9 A11
RES WE
A13 A8 A9 A11
CE
OE
Rev.5.00, Nov. 17.2003, page 2 of 22
HN58V256A Series, HN58V257A Series
Pin Description
Pin name A0 to A14 I/O0 to I/O7 OE CE WE VCC VSS RDY/Busy* RES* NC Note:
1 1
Function Address input Data input/output Output enable Chip enable Write enable Power supply Ground Ready busy Reset No connection
1. This function is supported by only the HN58V257A series.
Block Diagram
Note: 1. This function is supported by only the HN58V257A series.
VCC VSS I/O0 High voltage generator
to
I/O7
RDY/Busy *1
RES *1 OE CE WE RES *1
A0
to
I/O buffer and input latch Control logic and timing
Y decoder
Y gating
A5 Address buffer and latch A6
to
X decoder
Memory array
A14
Data latch
Rev.5.00, Nov. 17.2003, page 3 of 22
HN58V256A Series, HN58V257A Series
Operation Table
Operation Read Standby Write Deselect Write inhibit Data polling Program reset CE VIL VIH VIL VIL x x VIL x OE VIL x*
2
WE VIH x VIL VIH VIH x VIH x
RES* RES VH* x VH VH x x VH VIL
1
3
RDY/Busy Busy* Busy High-Z High-Z
3
I/O Dout High-Z Din High-Z Data out (I/O7) High-Z
VIH VIH x VIL VIL x
High-Z to VOL High-Z VOL High-Z
Notes: 1. Refer to the recommended DC operating condition. 2. x: Don't care 3. This function is supported by only the HN58V267A series.
Absolute Maximum Ratings
Parameter Supply voltage relative to VSS Input voltage relative to VSS Operating temperature range* Storage temperature range
2
Symbol VCC Vin Topr Tstg
Value -0.6 to +7.0 -0.5* to +7.0*
1 3
Unit V V C C
0 to +70 -55 to +125
Notes: 1. Vin min = -3.0 V for pulse width 50 ns 2. Including electrical characteristics and data retention 3. Should not exceed VCC + 1.0 V.
Recommended DC Operating Conditions
Parameter Supply voltage Input voltage Symbol VCC VSS VIL VIH VH* Operating temperature Notes: 1. 2. 3. 4.
4
Min 2.7 0 -0.3* 1.9* 0
2 1
Typ 3.0 0
Max 5.5 0 0.6
3
Unit V V V V C
VCC + 0.3* V VCC + 1.0 +70
VCC -0.5
Topr
VIL min: -1.0 V for pulse width 50 ns. VIH min for VCC = 3.6 to 5.5 V is 2.4 V. VIH max: VCC + 1.0 V for pulse width 50 ns. This function is supported by only the HN58V257A series.
Rev.5.00, Nov. 17.2003, page 4 of 22
HN58V256A Series, HN58V257A Series
DC Characteristics (Ta = 0 to +70C, VCC = 2.7 to 5.5 V)
Parameter Input leakage current Output leakage current Standby VCC current Operating VCC current Symbol ILI ILO ICC1 ICC2 ICC3 Min Output low voltage Output high voltage Note: VOL VOH VCC x 0.8 Typ Max 2* 2 20 1 8 12 12 30 0.4
1
Unit A A A mA mA mA mA mA V V
Test conditions VCC = 5.5 V, Vin = 5.5 V VCC = 5.5 V, Vout = 5.5/0.4 V CE = VCC CE = VIH Iout = 0 mA, Duty = 100%, Cycle = 1 s, VCC = 3.6 V Iout = 0 mA, Duty = 100%, Cycle = 1 ns, VCC = 5.5 V Iout = 0 mA, Duty = 100%, Cycle = 120 s, VCC = 3.6 V Iout = 0 mA, Duty = 100%, Cycle = 120 ns, VCC = 5.5 V IOL = 2.1 mA IOH = -400 A
1. ILI on RES = 100 A max (only the HN58V257A series)
Capacitance (Ta = +25C, f = 1 MHz)
Parameter Input capacitance* Note:
1 1
Symbol Cin Cout
Min
Typ
Max 6 12
Unit pF pF
Test conditions Vin = 0 V Vout = 0 V
Output capacitance*
1. This parameter is periodically sampled and not 100% tested.
Rev.5.00, Nov. 17.2003, page 5 of 22
HN58V256A Series, HN58V257A Series
AC Characteristics (Ta = 0 to +70C, VCC = 2.7 to 5.5 V)
Test Conditions * Input pulse levels: 0.4 V to 2.4 V (VCC 3.6V), 0.4V to 3.0 V (VCC > 3.6 V), 0 V to VCC (RES pin* )
2
* Input rise and fall time: 5 ns * Input timing reference levels: 0.8, 1.8 V * Output load: 1TTL Gate +100 pF * Output reference levels: 1.5 V, 1.5 V Read Cycle
HN58V256A/HN58V257A -12 Parameter Address to output delay CE to output delay OE to output delay Address to output hold OE (CE) high to output float* RES low to output float* RES to output delay*
2 1, 2 1
Symbol tACC tCE tOE tOH tDF tDFR tRR
Min 10 0 0 0 0
Max 120 120 60 40 350 600
Unit ns ns ns ns ns ns ns
Test conditions CE = OE = VIL, WE = VIH OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = OE = VIL, WE = VIH
Rev.5.00, Nov. 17.2003, page 6 of 22
HN58V256A Series, HN58V257A Series Write Cycle
Parameter Address setup time Address hold time CE to write setup time (WE controlled) CE hold time (WE controlled) WE to write setup time (CE controlled) WE hold time (CE controlled) OE to write setup time OE hold time Data setup time Data hold time WE pulse width (WE controlled) CE pulse width (CE controlled) Data latch time Byte load cycle Byte load window Write cycle time Time to device busy Write start time Reset protect time* Reset high time*
2, 6 2
Symbol tAS tAH tCS tCH tWS tWH tOES tOEH tDS tDH tWP tCW tDL tBLC tBL tWC tDB tDW tRP tRES
Min* 0 50 0 0 0 0 0 0 70 0 200 200 100 0.3 100 120 0* 1
5
3
Typ
Max -- 30 10*
4
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s ms ns ns s s
Test conditions
100
Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. This function is supported by only the HN58V257A series. 3. Use this device in longer cycle than this value. 4. tWC must be longer than this value unless polling techniques or RDY/Busy (only the HN58V257A series) are used. This device automatically completes the internal write operation within this value. 5. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy (only the HN58V257A series) are used. 6. This parameter is sampled and not 100% tested. 7. A6 through A14 are page addresses and these addresses are latched at the first falling edge of WE. 8. A6 through A14 are page addresses and these addresses are latched at the first falling edge of CE. 9. See AC read characteristics.
Rev.5.00, Nov. 17.2003, page 7 of 22
HN58V256A Series, HN58V257A Series
Timing Waveforms
Read Timing Waveform
Address tACC
CE
tCE
tOH
OE
tOE tDF
WE
Data Out
High
Data out valid tRR tDFR
RES *2
Rev.5.00, Nov. 17.2003, page 8 of 22
HN58V256A Series, HN58V257A Series Byte Write Timing Waveform (1) (WE Controlled)
tWC Address tCS tAH tCH
CE
tAS tWP tOES tBL
WE
tOEH
OE
tDS Din tDW RDY/Busy *2 High-Z tRP tDB High-Z tDH
tRES
RES *2
VCC
Rev.5.00, Nov. 17.2003, page 9 of 22
HN58V256A Series, HN58V257A Series Byte Write Timing Waveform (2) (CE Controlled)
Address tWS tAH tCW tAS tWH tBL tWC
CE
WE
tOES tOEH
OE
tDS Din tDW RDY/Busy *2 High-Z tRP tRES tDB High-Z tDH
RES *2
VCC
Rev.5.00, Nov. 17.2003, page 10 of 22
HN58V256A Series, HN58V257A Series Page Write Timing Waveform (1) (WE Controlled)
*7
Address A0 to A14
tAS
tAH tWP tDL tBLC
tBL
WE
tCS
tCH
tWC
CE
tOES tOEH tDH tDS
OE
Din
RDY/Busy *2
High-Z
tDB
tDW High-Z
tRP
RES *2
VCC
tRES
Rev.5.00, Nov. 17.2003, page 11 of 22
HN58V256A Series, HN58V257A Series Page Write Timing Waveform (2) (CE Controlled)
*8
Address A0 to A14
tAS
tAH tCW tDL tBLC
CE
tWS
tBL
tWH
tWC
WE
tOEH tOES
OE
Din
tDH tDS
RDY/Busy *2
High-Z
tDB
tDW High-Z
tRP
RES *2
VCC
tRES
Rev.5.00, Nov. 17.2003, page 12 of 22
HN58V256A Series, HN58V257A Series Data Polling Timing Waveform
Address
An
An
An
CE WE OE
tOE*9 I/O7 Din X Dout X Dout X tWC tDW tCE *9
tOEH
tOES
Rev.5.00, Nov. 17.2003, page 13 of 22
HN58V256A Series, HN58V257A Series Toggle bit This device provide another function to determine the internal programming cycle. If the EEPROM is set to read mode during the internal programming cycle, I/O6 will charge from "1" to "0" (toggling) for each read. When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible for next read or program. Toggle bit Waveform Notes: 1. I/O6 beginning state is "1". 2. I/O6 ending state will vary. 3. See AC read characteristics. 4. Any address location can be used, but the address must be fixed.
Next mode
*4
Address
CE WE OE
tOEH
tCE *3
tOE
*3
tOES
*1 *2 *2
I/O6
Din
Dout
Dout tWC
Dout
Dout tDW
Rev.5.00, Nov. 17.2003, page 14 of 22
HN58V256A Series, HN58V257A Series Software Data Protection Timing Waveform (1) (in protection mode)
VCC
+9tBLC Address Data 5555 AA 2AAA 55 5555 A0 Write address Write data tWC
Software Data Protection Timing Waveform (2) (in non-protection mode)
VCC
tWC
Normal active mode
+9Address Data 5555 2AAA 5555 5555 2AAA 5555 AA 55 80 AA 55 20
Rev.5.00, Nov. 17.2003, page 15 of 22
HN58V256A Series, HN58V257A Series
Functional Description
Automatic Page Write Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write cycle. Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each additional byte load cycle must be started within 30 s from the preceding falling edge of WE or CE. When CE or WE is high for 100 s after data input, the EEPROM enters write mode automatically and the input data are written into the EEPROM. Data Polling Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read mode during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the EEPROM is performing a write operation. RDY/Busy Signal (only the HN58V257A series) Busy RDY/Busy signal also allows the status of the EEPROM to be determined. The RDY/Busy signal has high impedance except in write cycle and is lowered to VOL after the first write signal. At the end of a write cycle, the RDY/Busy signal changes state to high impedance. RES Signal (only the HN58V257A series) When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping RES low when VCC is switched. RES should be high during read and programming because it doesn't provide a latch function.
VCC
Read inhibit
Read inhibit
4-5
Program inhibit Program inhibit
Rev.5.00, Nov. 17.2003, page 16 of 22
HN58V256A Series, HN58V257A Series WE, WE CE Pin Operation During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising edge of WE or CE. Write/Erase Endurance and Data Retention Time The endurance is 10 cycles in case of the page programming and 10 cycles in case of the byte programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is page4 programmed less than 10 cycles. Data Protection To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 20 ns or less. 1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to programming mode by mistake. Be careful not to allow noise of a width of more than 20 ns on the control pins.
5 4
WE CE
VIH 0V
OE
VIH 0V
20 ns max
Rev.5.00, Nov. 17.2003, page 17 of 22
HN58V256A Series, HN58V257A Series 2. Data Protection at VCC On/Off When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state. Note: The EPROM should be kept in unprogrammable state during VCC on/off by using CPU RESET signal.
VCC CPU RESET * Unprogrammable
* Unprogrammable
2.1 Protection by CE, OE, WE To realize the unprogrammable state, the input level of control pins must be held as shown in the table below.
CE OE WE x: Don't care. VCC: Pull-up to VCC level. VSS: Pull-down to VSS level. VCC x x x VSS x x x VCC
2.2 Protection by RES (only the HN58V257A series) The unprogrammable state can be realized by that the CPU's reset signal inputs directly to the EEPROM's RES pin. RES should be kept VSS level during VCC on/off. The EEPROM breaks off programming operation when RES becomes low, programming operation doesn't finish correctly in case that RES falls low during programming operation. RES should be kept high for 10 ms after the last data input.
VCC
4-5
Program inhibit Program inhibit
9or +-
1 s min 100 s min
10 ms min
Rev.5.00, Nov. 17.2003, page 18 of 22
HN58V256A Series, HN58V257A Series 3. Software data protection To prevent unintentional programming, this device has the software data protection (SDP) mode. The SDP is enabled by inputting the following 3 bytes code and write data. SDP is not enabled if only the 3 bytes code is input. To program data in the SDP enable mode, 3 bytes code must be input before write data.
Address Data
5555 AA 2AAA 55 5555 A0 Write address Write data } Normal data input
The SDP mode is disabled by inputting the following 6 bytes code. Note that, if data is input in the SDP disable cycle, data can not be written.
Address 5555 2AAA 5555 5555 2AAA 5555 Data AA 55 80 AA 55 20
The software data protection is not enabled at the shipment. Note: There are some differences between Renesas Technology's and other company's for enable/disable sequence of software data protection. If there are any questions , please contact with Renesas Technology's sales offices.
Rev.5.00, Nov. 17.2003, page 19 of 22
HN58V256A Series, HN58V257A Series
Package Dimensions
HN58V256AFP Series (FP-28D, FP-28DV)
Unit: mm
18.3 18.8 Max 28 15
8.4
1.12 Max
*0.17 0.05 0.15 0.04
1
14
2.50 Max
11.8 0.3 1.7 0 - 8
1.27 0.15
*0.40 0.08 0.38 0.06
0.20 0.10
1.0 0.2
0.20 M
*Dimension including the plating thickness Base material dimension
Package Code JEDEC JEITA Mass (reference value)
FP-28D, FP-28DV Conforms -- 0.7 g
Rev.5.00, Nov. 17.2003, page 20 of 22
HN58V256A Series, HN58V257A Series
Package Dimensions (cont.)
HN58V256AT Series (TFP-28DB, TFP-28DBV)
Unit: mm
8.00 8.20 Max 28 15
1
14 0.55
*0.22 0.08 0.10 M 0.20 0.06 0.45 Max
11.80
13.40 0.30 0 - 5
0.80
*0.17 0.05 0.15 0.04
1.20 Max
0.10
0.13 -0.08
+0.07
0.50 0.10
*Dimension including the plating thickness Base material dimension
Package Code JEDEC JEITA Mass (reference value)
TFP-28DB, TFP-28DBV -- -- 0.23 g
Rev.5.00, Nov. 17.2003, page 21 of 22
HN58V256A Series, HN58V257A Series
Package Dimensions (cont.)
HN58V257AT Series (TFP-32DA, TFP-32DAV)
Unit: mm
8.00 8.20 Max 32 17
1
16 0.50
*0.22 0.08 0.20 0.06
0.08 M 14.00 0.20 0 - 5 0.50 0.10 0.80
0.45 Max
12.40
0.10
*0.17 0.05 0.125 0.04
0.13 0.05
1.20 Max
*Dimension including the plating thickness Base material dimension
Package Code JEDEC JEITA Mass (reference value)
TFP-32DA, TFP-32DAV Conforms Conforms 0.26 g
Rev.5.00, Nov. 17.2003, page 22 of 22
Revision History
Rev. Date
HN58V256A/HN58V257A Series Data Sheet
Contents of Modification Page Description Initial issue Determination of package type: HN58V256AT series (TFP-28DB) Deletion of HN58V256AP series (DP-28) Deletion of HN58V256AFPI-12/15 Deletion of HN58V256AT-12SR/15SR Deletion of HN58V257AT-12SR/15SR Absolute Maximum Rating Deletion of Device Group Deletion of Operating temperature range - 20 to + 85C and - 40 to +85C Recommended DC Operating Conditions Deletion of Device Group Deletion of Operating temperature range -20//85C and -40//85C Deletion of note 4 Change order of notes Change of format Operating Information Deletion of HN58V256A-15 and HN58V257A-15 Deletion of note 1 Deletion of Compatible type No. Deletion of Operating temperature range Pin Description Addition of note 1 Block Diagram Addition of note 1 Mode Selection Addition of note 3 Absolute Maximum Ratings Addition of note 4 Recommended DC operating Condition VIH (min) 2.4 V to 1.9 V Addition of note 4 DC Characteristics ICC3 (max): 8/12/20/30 mA to 8/12/15/30 mA AC Characteristics Test condition: Input pulse levels: 0 V to 3.0 V to 0.4 V to 2.4 V(VCC 3.6 V), 0.4 V to 3.0 V(VCC > 3.6V) Addition of note 2 Read Timing Waveform: Addition of note 1 Write Cycle: tDS (min): 50 ns to 70 ns Addition of note 4, 5 Byte Write Timing Waveform (1) and (2): Addition of note 1 Page Write Timing Waveform (1) and (2): Addition of note 2 4
0.0 0.1
Mar. 15. 1995 Aug. 7. 1995
4
1.0
Apr. 12. 1995
2
3 3 4 4
5 6
Revision Record (cont.)
Rev. Date Contents of Modification Page 1.0 Apr. 12. 1995 6 Description Timing Waveforms Data Polling Timing Waveform: Addition of note 1 Toggle bit Waveform: Addition of note 4 Functional Description Data Protection 2-(2) Addition of figure Functional Description Data protection 3: Addition of note Functional Description Data protection 3: Change of Description Timing Waveforms Read Timing Waveform: Correct error
16 2.0 3.0 4.0 5.00 Mar. 4. 1997 May. 20. 1997 Oct. 24. 1997 Nov. 17. 2003 16 16 8 2
Change format issued by Renesas Technology Corp. Ordering Information Addition of HN58V256AFP-12E, HN58V256AT-12E, HN58V257AT-12E 20-22 Package Dimensions FP-28D to FP-28D, FP-28DV TFP-28DB to TFP-28DB, TFP-28DBV TFP-32DA to TFP-32DA, TFP-32DAV
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001
http://www.renesas.com
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